IP-Address Lookup Using Hardware Pipelining

Fast IP address lookup mechanism is a major design issue for the next generation routers. The existing scheme performs the IP address lookup by hardware in which the forwarding table can be compressed to fit into reasonable-size SRAM, and a lookup can be accomplished in three memory accesses. In this article, we claim that with a little extra memory, it is able to further reduce the lookup time to two memory accesses. Moreover, it can be implemented in pipelined hardware so that one routing lookup per memory access can be achieved. With state-of-the-art SRAM technology, this mechanism can achieve more than 100 million routing lookups per second. KEYWORD: Internet, Address Lookup, Pipelining INTRODUCTION Speeding up the packet forwarding in the Internet backbone requires high-speed transmission links and high performance routers. The transmission technology keeps evolving and provision of gigabit fiber links is readily available. Consequently, the key to increase the capacity of the Internet lies on fast routers [7]. A multi-gigabit router must have enough internal bandwidth to switch packets between its interfaces at multi-gigabit rates, and enough packet processing power to forward multiple millions of packets per second (MPPS). Switching in the router has been studied extensively in the ATM community and solutions for fast packet processing are commercially available. As a result, the major remaining bottleneck for the Internet router design is the slow, software-based IP lookup procedures. It is inappropriate to accomplish IP lookup for the next generation routers through software, further investigation to resolve the issue is an important and highly challenged task. An IP lookup scheme is the most fundamental operation in any IP routing product. A packet carries a specific IP Destination Address (DA), which is a unique 32-bit field in current IP version 4 implementations. A router must search forwarding tables using a DA as the key, and determine which table entry represents the best route to forward the packet to its destination. Since the development of CIDR in 1993 [8], IP routes have been identified by a pair, where the prefix length ranges from 1 to 32 bits. For every incoming packet, a search in the router’s forwarding table must be performed to determine which next hop the packet should be destined for. With CIDR, the search may be decomposed into two steps. First, it needs to find the set of routes with prefixes matching that of the incoming destination IP address. Then, among this set of routes, it has to select the one with the longest matched prefix. This is the route used to identify the next hop. Due to the facts that table entries have variable lengths and that multiple entries may represent the valid routes to the same destination, the search may be complicated. Since IPv6 is still some way off, IPv4 will stay for a while. Thus, we focus on the hardware scheme optimized for IPv4 routing lookups. This work presents a fast longest prefix matching scheme for IP switch routers. Based on our proposed scheme, the forwarding table would be reduced to enough small to fit into SRAM with very low cost. Most of the address lookups can be accomplished in a single memory access. In the worst case, the number of memory accesses for a lookup is two. When implemented in pipelined hardware, the proposed scheme can achieve one routing lookup per memory access. With state-of-the-art SRAM technology, this mechanism can achieve more than 100 million routing lookups per second. The rest of the paper is organized as follows. Section 1 describes the previous work. The proposed longest prefix matching scheme and the hardware architecture is presented in Section 2. The performance analysis of the proposed scheme is addressed in Section 3. Finally, a conclusion remark is given in Section 4. 1. RELATED WORKS Several works have been proposed with novel data structures to reduce the complexity of longest-prefix matching lookups [2][9][11]. These data structures and their accompanying algorithms are designed primarily for software implementations, they are usually unable to complete a lookup in few memory accesses. The most straightforward way to implement a lookup scheme is to build a forwarding table for all possible IP addresses. However, the size of the forwarding table (next-hop array; NHA) is too large (2 entries) to be practical. To reduce the size of the forwarding table, an indirect lookup mechanism, as shown in Fig. 1 [3], can be employed. Each IP address is split into two parts: the segment (16-bit) and the offset (16-bit). The segment table has 64 K entries which record either the next hop of the route or pointers pointing to the associated NHAs. Each NHA consists of 64K entries, each entry records the next hop for the destination IP address. This scheme achieves a maximum of two memory accesses for a lookup in a 33-Mbyte forwarding table. By adding an intermediate-length table, the forwarding table can be reduced to 9 Mbytes; however, the maximum number of memory accesses for a lookup would be increased to three. When implemented in hardware pipeline, the scheme can accomplish one route lookup every memory access and achieve up to 20 million lookups per second. 16 bits 32 bits IP address